The present invention relates to a computer system, and more particularly, to an extended bus controller suitable for improving the efficiency of data transfer via a plurality of busses.
An extended bus controller has a base module and an extension module, the former module including a central processing and controlling unit connected to a base bus, a memory unit, and peripheral control units, and the latter module including peripheral control units connected to an extended bus. Such a conventional extended bus controller is disclosed, for example, in Japanese Patent Laid-open Publication No. JP-A-57-34234. In the conventional extended bus controller, data transfer between the peripheral control units and the memory unit within the base module is conducted in synchronism with a synchronous clock signal from the central processing and controlling unit. On the other hand, data transfer between the peripheral control units and the memory unit within the extension module is conducted in synchronism with another synchronous clock signal having a lower frequency than that of the first-mentioned synchronous clock signal, the synchronous clock signal having the lower frequency being obtained by masking a predetermined number of synchronous clocks of the first-mentioned clock signal for the time corresponding to a delay time of data transmission between the peripheral control units and the memory unit within the extension module.
The above-described conventional technique poses the following problems. As the synchronous clock signal to be used in accessing the peripheral control units and the memory unit within the extension module, a synchronous clock signal which is derived from the synchronous clock signals on the base bus by adjusting it in units of its peripheral clock can only be obtained. Therefore, the efficiency of data transfer between the peripheral control units and the memory unit within the extension module cannot be optimized. Further, it is required that a circuit for masking the synchronous clock signal be prepared.